The invention relates generally to computer systems, and more particularly to computer system bus protocols. As it is known in the art, computer systems generally include one or more nodes coupled to a system bus. The nodes can be of several types. Processor nodes generally include one or more CPUs which may have local caches associated with them. I/O nodes provide data transfer between the system bus and any of several I/O protocols for supporting various I/O devices such as hard disk drives and network interfaces. Memory nodes include one or several banks of dynamic RAM for access by the processor nodes and the I/O nodes.
Because the system bus is utilized in virtually every inter-node operation performed by the computer system, it is a key element whose characteristics have a major impact on the overall performance of the system. For instance, the speed at which the system bus is capable of transferring information from one node to another is a critical factor contributing to system performance. Presently used non-pended system busses typically employ a single bus protocol wherein a bus transaction has an address portion and a data portion, and wherein the contents and timing of each portion are varied depending upon the type of bus transaction occurring. These busses might be multiplexed, such that the address and data signals share the same bus signal lines during different time slots, or they might be de-multiplexed, wherein address signals and data signals are driven on separate bus signal lines. In either case, the typical protocol consists of a period of time for which address and command information is asserted on the bus by a node, followed by a period of time for which data is driven on the bus by a node, followed by a period of time in which new address and command information may be asserted by a node, etc. That is, the address and data portions of the protocol are dependent upon the completion of the preceding data or address portion.
The interdependency of the address and data portions of the typical system bus protocol can adversely affect the overall performance of the bus. For instance, where two nodes desire to initiate a transaction on a non-pipelined bus, both the address portion and the data portion of the bus protocol (and any overhead associated with each) must be completed for one node before the address portion may commence for the other node. On a pipelined bus, the address portion of a transaction may overlap the data portion of a previous transaction; however, time periods during which address portions and data portions may occur on the bus remain rigidly slotted and interdependent.
System performance can also be adversely affected by the bus flow control mechanisms provided. In the typical bus protocol where a bus transaction includes an address portion followed by a data portion, there is sometimes provided a flow control signal for affecting the length of time the data portion will last. Assertion of this flow control signal affects both the data portion of a cycle and the frequency with which address portions of cycles may be submitted to the bus, since data portions associated with the new address portions cannot be executed until the previous data portion completes. Node access to the bus is thereby adversely restricted.